Silimate is the co-pilot for chip designers.

Chip teams today are still using the same archaic workflows from 30 years ago, resulting in lengthy 12-18 month design cycles and the inability to ship chips fast enough to keep up with the software pointer.

We're changing that at Silimate.

Our chip design co-pilot is helping chip designers write correct, PPA-optimized RTL code from the onset, and build better chips in less time. We're building a catalytic tool for the chip industry.

We're well-funded by top investors and are generating revenue with customers that are world-class chip and IP design companies. We're growing fast — demand for Silimate has outpaced our ability to build and ship the product. We're looking for talented engineers that are passionate about the semiconductor chip space to join us.

We’re growing the team further! We’re looking for a passionate founding engineer who has significant experience with the VLSI front-end design flow and strong coding skills to join our growing team and build the co-pilot for chip designers with us.

Who you are:

You’re excited about transforming the way chips are built by the entire industry, and enabling new levels of dynamism and speed for the hardware compute ecosystem.

You’ll leverage your understanding of functional correctness and PPA optimization in RTL design to develop key co-pilot features that make building chips much faster, easier, and more intuitive.

You’ll also work directly with our world-class customers building advanced chips and IP to iterate on our product with user feedback.

We ship product updates on a weekly basis, work in-person together in the Bay Area, and geek out about semiconductor news/technology advances. If this sounds like you, please apply to join the team!

What you’ll do:

• Write code (Python/C++) that ships to Silimate’s 10+ chip/IP customers
• Make software architectural decisions for key product features
• Translate user feedback to product updates/features
• Plan core product roadmap and strategy with the founders

Minimum requirements:

• Passionate and excited about chips and AI for EDA
• Have experience designing ASICs using SystemVerilog and synthesis/verification tools (open-source and/or commercial)
• Good at writing/shipping high-quality code (Python/C++) quickly
• Basic knowledge of statistics & AI/ML methods
• Resilient, data-driven, and works from first principles

Ideal requirements:

• 1+ tapeouts (ideally on advanced technology nodes)
• Contributor to open-source EDA/chip efforts
• Significant experience with PPA optimization and/or functional correctness convergence

Benefits:

• Generous salary and equity package
• Full health/vision/dental/401k benefits